In the prior art, there is the wiring substrate on which an electronic component such as a semiconductor chip, or the like is mounted. In an example of such wiring substrate, the build-up wiring is formed on one surface or both surfaces of the core substrate by the semi-additive process, or the like.
In recent years, with the enhancement in performances of an electronic component such as a semiconductor chip, or the like, a narrower pitch between wiring layers in the wiring substrate is advanced.
A related art is disclosed in Japanese Laid-open Patent Publication No. 11-87931.
In the formation of the wirings by using the semi-additive process, as a surface roughness of the insulating resin layer is increased, adhesion of the wiring layers formed on the insulating resin layer can be improved, nevertheless unevenness on the insulating resin layer brings about an obstacle upon forming the fine wiring layers. When the unevenness is produced on a surface of the insulating resin layer, an electric short-circuit due to the residue at the time in removing a seed layer occurs easily between the wirings.